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2010-2012 Microchip Technology Inc.

DS41417B-page 153

PIC16(L)F722A/723A

16.4

AUSART Operation During Sleep

The AUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore can not generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

16.4.1

SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception

(refer to Section 16.3.2.4 “Synchronous Slave

Reception Set-up:”).

If interrupts are desired, set the RCIE bit of the

PIE1 register and the PEIE bit of the INTCON

The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set, thereby waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit of the INTCON register is

also set, then the Interrupt Service Routine at address

0004h will be called.

16.4.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Transmission

(refer to Section 16.3.2.2 “Synchronous Slave

Transmission Set-up:”).

The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set, thereby waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

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